Ultra low power wide range four quadrant analog multiplier

Abstract

A novel four quadrant FGMOS analog multiplier having properties such as low voltage-low power and wide input linearity range is presented. Power consumption of the proposed multiplier is 26.2 nW and the input swing is rail-to-rail which is obtained by choosing the ratio of input capacitances to total capacitance of FGMOS transistors resulting a reduction in the transconductance. Other important features of the proposed multiplier are the bandwidth of 52.5 MHz and maximum THD of 2.04% (when the input voltages are at supply voltage level).