Determining the potential barrier presented by the interfacial layer from the temperature induced I-V characteristics in Al/p-Si Structure with native oxide layer

Abstract

The temperature induced current-voltage (I-V-T) characteristics of the Al/SiO2/p-Si diodes with the interfacial native oxide layer were experimentally investigated in present our study. The values of 24.35 and 1.02 eV for the tunneling factor (a delta(root chi)) and the potential barrier presented by the interfacial layer (chi) were determined for the Al/SiO2/p-Si metal-insulator-semiconductor (MIS) diode. The chi value obtained from the forward bias I-V-T characteristics of the SiO2/p-Si diode is a crucial result according to those from only room temperature I-V curves in literature studies. Furthermore, the temperature dependence of the apparent barrier heights of the forward bias I-V-T characteristics displayed a Gaussian distribution (GD) of inhomogeneous barrier heights (BHs). Thus, the standard deviation values of sigma 1(s)(0) = 147.65 mV for high temperature range and sigma 2(s)(0) = 83.66 mV for low temperature range were obtained from the GD plot of the BHs (the apparent BH versus (2kT)(-1) plot). Again, for the mean barrier height (Phi) over bar (b0) from the GD plot of the BHs, the values of 1.16 eV and 0.70 eV were obtained from the high temperature region and low temperature region, respectively. Furthermore, the Richardson constant values of 54.66 and 58.42 A/K(2)cm(2) from these temperature regions are approximately 1.70 times higher than the theoretical value of 32 A/K(2)cm(2) of the p-type Si semiconductor.